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UID:pretalx-eu-summit-2026-MD7RVM@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T134000
DTEND;TZID=CET:20260609T135000
DESCRIPTION:We present the studies leading up to the temporal safety suppor
 t included in the RV64Y “CHERI” capability RISC-V extension. Memory sa
 fety enforcement is increasingly important for new programs\, languages\, 
 and architectures. RV64Y enforces spatial memory safety natively\, and pro
 vides the necessary invariants to enforce temporal safety in software.\nTo
  ensure that RV64Y systems can enforce temporal safety with reasonable per
 formance and memory overhead\, we have reproduced experiments from previou
 s CHERI research\, optimised CheriBSD revocation support\, and explored si
 mplified state machines for virtual memory pages encoded in Page Table Ent
 ry (PTE) bits.  We managed to optimize revocation in CheriBSD to reduce ov
 erhead in Spec2006 by 12%. We then explored the simplest PTE encoding with
  generational capability read support\, and found that they incurred an ov
 erhead of about 33% over the optimised baseline\, justifying the inclusion
  of generational capability dirty states in the frozen RV64Y specification
 . Finally\, we discuss ongoing work that has the potential to further opti
 mize temporal safety for RV64Y with vendor-specific or future ratified ext
 ensions.
DTSTAMP:20260522T163122Z
LOCATION:Poster Island A
SUMMARY:RV64Y Temporal Safety Exploration - Jonathan Woodruff
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/MD7RVM/
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