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UID:pretalx-eu-summit-2026-MKBAZS@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T104000
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DESCRIPTION:Assessing the vulnerability of caches against side-channel atta
 cks is of critical importance when enhanced microarchitectural security is
  a must-have feature for a multicore CPU implementation. Previous works ha
 ve proposed various metrics and methodologies to assess such vulnerabiliti
 es. However\, those works suffer from limitations regarding either the ran
 ge of target cache attacks\, the support for the RISC-V ISA\, or the publi
 c availability of the assessment tools. The goal of this paper is to provi
 de support for systematically evaluating RISC-V multicore CPUs against a w
 ide range of cache timing attacks. This support should allow the assessmen
 t of both real and simulated systems\, enabling early security evaluation 
 in the design phase of the processor using the open-source gem5 microarchi
 tectural simulator. We base our approach on the Cache Timing Vulnerability
  Score (CTVS) methodology and enhance it along two axes. We first port the
  CTVS methodology to the RISC-V ISA\, and then we integrate the CTVS metho
 dology for the RISC-V and x86 ISAs with gem5. We evaluate the use of the C
 TVS methodology for simulated RISC-V and x86 multicore CPUs and analyze th
 e results.
DTSTAMP:20260522T163536Z
LOCATION:Poster Island A
SUMMARY:Evaluating the Vulnerability of RISC-V CPUs Against Cache Timing At
 tacks - Vasileios Karakostas
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/MKBAZS/
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