Assessing the vulnerability of caches against side-channel attacks is of critical importance when enhanced microarchitectural security is a must-have feature for a multicore CPU implementation. Previous works have proposed various metrics and methodologies to assess such vulnerabilities. However, those works suffer from limitations regarding either the range of target cache attacks, the support for the RISC-V ISA, or the public availability of the assessment tools. The goal of this paper is to provide support for systematically evaluating RISC-V multicore CPUs against a wide range of cache timing attacks. This support should allow the assessment of both real and simulated systems, enabling early security evaluation in the design phase of the processor using the open-source gem5 microarchitectural simulator. We base our approach on the Cache Timing Vulnerability Score (CTVS) methodology and enhance it along two axes. We first port the CTVS methodology to the RISC-V ISA, and then we integrate the CTVS methodology for the RISC-V and x86 ISAs with gem5. We evaluate the use of the CTVS methodology for simulated RISC-V and x86 multicore CPUs and analyze the results.