A Proof-of-Concept RISC-V with 128-bit Extension
2026-06-10 , Plenary

Addressing ever-larger amounts of memory is a fact of (computerized) life. The authors of the RISC-V unpriviledge specification did recognize that and coined on less than one and a half page what could be a natural extension to 128-bit of the 32- and 64-bit RISC-V ISA. Given this RV128I draft, we (a) defined an ELF128 extension for binaries, (b) made gnu-based a cross-compilation environment able to use RV128I instructions and generate ELF128 binaries, (c) added support for this extension and ELF128 in QEMU, (d) added the necessary instructions and resources in the CVA6 processor.