2026-06-10 –, Plenary
In this session RISC-V’s Chief Architect will give an overview of RISC-V adoption across computing markets from Embedded to AI. Krste will discuss new developments in the RISC-V ISA, including security extensions and matrix extensions for AI, as well as new profile and platform initiatives.
Krste Asanović is Professor Emeritus and a Professor of the Graduate School in the EECS Department at UC Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998, then joined the faculty at MIT, receiving tenure in 2005. He returned to Berkeley in 2007, where he co-founded the Berkeley Parallel Computing Laboratory, led the ASPIRE Lab, and co-led the ADEPT Lab and Berkeley SLICE Lab. His main research areas are computer architecture, VLSI design, parallel programming, and operating system design.
He has led the RISC-V open ISA project at Berkeley from its inception in 2010 and co-founded the RISC-V Foundation in 2015, which has now become RISC-V International, where he serves as Chief Architect. He also co-founded SiFive in 2015 to commercialize RISC-V processors, serving as Chief Architect there. He is an ACM Fellow and an IEEE Fellow.