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UID:pretalx-eu-summit-2026-NEMJHQ@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T140000
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DESCRIPTION:This work introduces a compatible acceleration approach for AES
  encryption that retains the standardized ISA interface while enhancing ex
 ecution time for AES-128 on 32-bit processors\, including the key-schedule
  phase. By reformulating the behavior of existing Zk instructions without 
 altering their opcodes\, we preserve binary and source compatibility with 
 software written for Zkne\, without the performance losses of having to pe
 rform key expansion only by software. The result is an integration strateg
 y suitable for constrained IoT or automotive devices that delivers improve
 d throughput with reduced area overhead\, enabling systems to realize the 
 intended benefits of RISC-V’s cryptographic extension without sacrificin
 g portability and standarization.
DTSTAMP:20260522T163929Z
LOCATION:Poster Island B
SUMMARY:Integrating AES Cryptographic Acceleration with RISC-V Cryptography
  Extensions in 32-bit processors - Francisco J. Romero
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/NEMJHQ/
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