2026-06-09 –, Poster Island B
This work introduces a compatible acceleration approach for AES encryption that retains the standardized ISA interface while enhancing execution time for AES-128 on 32-bit processors, including the key-schedule phase. By reformulating the behavior of existing Zk instructions without altering their opcodes, we preserve binary and source compatibility with software written for Zkne, without the performance losses of having to perform key expansion only by software. The result is an integration strategy suitable for constrained IoT or automotive devices that delivers improved throughput with reduced area overhead, enabling systems to realize the intended benefits of RISC-V’s cryptographic extension without sacrificing portability and standardization.
Francisco J. Romero received the B.Eng. in Telecommunications Engineering from the University of Granada (UGR, Spain) in 2016 and the M.Eng. in Telecommunications Engineering from the same university in 2018, both with Extraordinary Awards. In 2015, he joined the Department of Electronics and Computer Technology at UGR as an undergraduate researcher, where he began working on embedded systems and wearable devices, later expanding his research to emerging technologies for IoT applications. In 2021, he obtained his PhD with honors in collaboration with the Institute for Nanoelectronics at the Technical University of Munich (TUM, Germany). He also completed several industrial research stays at Infineon Technologies AG and eesy-innovation GmbH, contributing to multiple technology-transfer projects. He is currently an Associate Professor at UGR, where his research focuses on embedded systems, hardware-based security, and memristive and emerging electronic technologies.