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UID:pretalx-eu-summit-2026-NMX7W7@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T103000
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DESCRIPTION:The Sail RISC-V Model can generate an executable file from its 
 formal specification\,. Currrently RISC-V tests only provides limited test
  cases and cannot comprehensively test your RISC-V implementation. Some ch
 ips may use self-developed simulators for testing\, but they cannot obtain
  formal verification-based guarantees like RISC-V Sail Model\, nor can the
 y offer full configurability. This work introduces a new test framework th
 at uses the RISC-V Sail Model as the ref model\, ensuring the model's comp
 leteness and accuracy. To improve simulation performance\, we choose to us
 e Pydrofoil\, which is an improved version of the Sail Model that delivers
  ultra-high performance. To enhance test compatibility and usability\, we 
 provide a set of simple test interfaces (including register access\, memor
 y access\, etc.) and support customizing model configurations. Currently\,
  it has successfully integrated tests for some open-source RISC-V implemen
 tations.
DTSTAMP:20260522T163252Z
LOCATION:Poster Island A
SUMMARY:An Efficient Approach to Apply the RISC-V Sail Model to Chip Verifi
 cation - Mingzhu Yan\, Yunxiang Luo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/NMX7W7/
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