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UID:pretalx-eu-summit-2026-PB9JGQ@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T135000
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DESCRIPTION:This paper provides a quantitative analysis of the costs and be
 nefits of integrating a dedicated hardware accelerator for the Post Quantu
 m Cryptography (PQC) algorithm ML-KEM into a 32-bit RISC-V SoC. We compare
  a software-only implementation on the CV32E40P core against a full-hardwa
 re datapath offloading the entire algorithm. We implemented the system on 
 a 22 nm ASIC chip\, and we measured the results: the dedicated hardware ac
 hieves a 139x speed-up over the software baseline. This performance gain r
 equires an area overhead of 301 kGE\, representing only a 6% increase in t
 he total SoC silicon footprint. This study provides a data-driven assessme
 nt of the silicon-to-latency trade-off for Post-Quantum Cryptography (PQC)
  in resource-constrained RISC-V systems.
DTSTAMP:20260522T163242Z
LOCATION:Poster Island B
SUMMARY:Cost-Benefit Analysis of a 22nm ASIC ML-KEM Accelerator for RISC-V 
 Secure Elements - Ivan Sarno\, Stefano Di Matteo\, Emanuele Valea\, Hack
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/PB9JGQ/
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