2026-06-09 –, Poster Island B
This paper provides a quantitative analysis of the costs and benefits of integrating a dedicated hardware accelerator for the Post Quantum Cryptography (PQC) algorithm ML-KEM into a 32-bit RISC-V SoC. We compare a software-only implementation on the CV32E40P core against a full-hardware datapath offloading the entire algorithm. We implemented the system on a 22 nm ASIC chip, and we measured the results: the dedicated hardware achieves a 139x speed-up over the software baseline. This performance gain requires an area overhead of 301 kGE, representing only a 6% increase in the total SoC silicon footprint. This study provides a data-driven assessment of the silicon-to-latency trade-off for Post-Quantum Cryptography (PQC) in resource-constrained RISC-V systems.
Stefano Di Matteo received his M.Sc. (2019) and Ph.D. (2023) respectively in Electronic Engineering and Information Engineering from the University of Pisa. He is currently a tenure-track researcher in hardware implementation of Post-Quantum Cryptography at CEA in Grenoble. His research interests include hardware implementation of PQC with countermeasures against physical attacks, RISC-V architectures, and Instruction Set Extensions for PQC
Ivan Sarno received the B.Sc. degree in Computer Science and the M.Sc. degree in Cybersecurity from the University of Pisa, Italy. He is currently pursuing the Ph.D. degree at the University of Grenoble Alpes, conducting his research at CEA List and TIMA Laboratory, Grenoble, France. His research focuses on secure hardware/software implementation of post-quantum cryptography on RISC-V platforms, including custom ISA extensions for cryptographic acceleration.
Emanuele Valea received the master’s degree in electronic engineering from the Politecnico di
Torino, Turin, Italy, in 2016, and the Ph.D. degree in microelectronics from the University of Montpellier,
Montpellier, France, in 2020. He is currently a Researcher at CEA LIST, Grenoble, France. His research interests include hardware security and trust, cryptographic primitives for microelectronics, and security-related aspects of VLSI testing and reliability.
