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UID:pretalx-eu-summit-2026-PTSN7C@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T112000
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DESCRIPTION:The evolution of modern computing towards emerging paradigms\, 
 such as In-Memory Computing (IMC)\, is severely limited by the high intrin
 sic noise of these memory technologies.\n        Simultaneously\, conventi
 onal Von Neumann architectures exhibit data-dependent execution and power 
 profiles\, leaving embedded systems highly vulnerable to physical Side-Cha
 nnel Attacks. \n        In this extended abstract\, we propose a novel par
 adigm based on Hyperdimensional Computing for encoding and decoding RISC-V
  instructions. By mapping standard assembly instructions into a neural-ins
 pired holographic representation and storing them in superposition\, lever
 aging the capacity of high-dimensional spaces\, the traditional decoding l
 ogic is replaced by a highly parallel Associative Memory. Our Design Space
  Exploration compares 1-bit Binary and 8-bit Integer representations\, eva
 luating the trade-off between instruction capacity (chunk size) and dimens
 ionality. Furthermore\, we demonstrate the intrinsic fault tolerance and s
 ecurity-by-design of the architecture: a binary HDC system maintains 100% 
 decoding accuracy even when subjected to a 5% physical memory corruption\,
  while its constant-time execution and massive pseudo-random switching act
 ivity inherently mask side-channel leakages. This paradigm paves the way f
 or ultra-robust\, secure\, and ECC-free RISC-V pipelines tailored for next
 -generation processing cores.
DTSTAMP:20260522T163128Z
LOCATION:Poster Island B
SUMMARY:Holographic Execution: A Hyperdimensional Computing Approach for Ro
 bust RISC-V Instruction Decoding - Marcello Barbirotta
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/PTSN7C/
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