The evolution of modern computing towards emerging paradigms, such as In-Memory Computing (IMC), is severely limited by the high intrinsic noise of these memory technologies.
Simultaneously, conventional Von Neumann architectures exhibit data-dependent execution and power profiles, leaving embedded systems highly vulnerable to physical Side-Channel Attacks.
In this extended abstract, we propose a novel paradigm based on Hyperdimensional Computing for encoding and decoding RISC-V instructions. By mapping standard assembly instructions into a neural-inspired holographic representation and storing them in superposition, leveraging the capacity of high-dimensional spaces, the traditional decoding logic is replaced by a highly parallel Associative Memory. Our Design Space Exploration compares 1-bit Binary and 8-bit Integer representations, evaluating the trade-off between instruction capacity (chunk size) and dimensionality. Furthermore, we demonstrate the intrinsic fault tolerance and security-by-design of the architecture: a binary HDC system maintains 100% decoding accuracy even when subjected to a 5% physical memory corruption, while its constant-time execution and massive pseudo-random switching activity inherently mask side-channel leakages. This paradigm paves the way for ultra-robust, secure, and ECC-free RISC-V pipelines tailored for next-generation processing cores.