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UID:pretalx-eu-summit-2026-PYSBZM@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T142000
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DESCRIPTION:In this paper\, we present the results of the XXXXXXXX project\
 , in which a fully open-source\, parametrizable low-power floating-point u
 nit (FPU) under HUB format has been designed and validated. This unit\, im
 plemented in SystemVerilog\, supports addition\, subtraction\, multiplicat
 ion\, division\, square root\, and Fused Multiply-Add (FMA) operations und
 er HUB format. This FPU has been exhaustively tested through simulation an
 d FPGA implementations. Moreover\, it has been integrated with some RISC-V
  cores and validated using several test benches. The development is comple
 mented by a compiler environment that enables native FPHUB arithmetic for 
 C and C++ programs. The proposed unit achieves a roughly 60\\% reduction i
 n area and power consumption compared with a classic IEEE FPU implementati
 on.
DTSTAMP:20260522T163243Z
LOCATION:Poster Island D
SUMMARY:Low-power Floating Point Unit for RISC-V Processors using FPHUB for
 mat - Javier Hormigo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/PYSBZM/
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