In this paper, we present the results of the XXXXXXXX project, in which a fully open-source, parametrizable low-power floating-point unit (FPU) under HUB format has been designed and validated. This unit, implemented in SystemVerilog, supports addition, subtraction, multiplication, division, square root, and Fused Multiply-Add (FMA) operations under HUB format. This FPU has been exhaustively tested through simulation and FPGA implementations. Moreover, it has been integrated with some RISC-V cores and validated using several test benches. The development is complemented by a compiler environment that enables native FPHUB arithmetic for C and C++ programs. The proposed unit achieves a roughly 60\% reduction in area and power consumption compared with a classic IEEE FPU implementation.