2026-06-10 –, Demo Theater
Verification has become one of the most time-consuming stages in modern high-performance processor development. Co-simulation compares the Design Under Test (DUT) against a reference model (REF) at instruction granularity, providing strong debuggability, but existing software-based solutions are limited to KHz-level speeds and cannot meet industrial-scale verification demands. FPGA platforms can accelerate processor simulation to tens of MHz; however, massive and frequent hardware-software communication between the FPGA-hosted DUT and software REF still constrains co-simulation throughput.
We present DiffTest-H, an FPGA-accelerated co-simulation framework for industrial-scale RISC-V processor verification. By exploiting the structural, ordering, and behavioral characteristics of verification data, DiffTest-H optimizes communication through compression and packaging while preserving instruction-level comparison and debugging capability. It reduces communication overhead by up to 99.7% with 3.2% additional area overhead on Xilinx VU19P, achieving co-simulation speeds beyond 10 MHz and enabling faster verification iteration.
DiffTest-H has been deployed to verify XiangShan, a high-performance out-of-order RISC-V processor, covering interrupts, memory hierarchy behaviors, vector extensions, and virtualization. Across FPGA and emulator platforms, it has helped uncover more than 151 complex bugs in XiangShan, demonstrating its effectiveness for large-scale industrial processor verification.
Yinan Xu is an Assistant Professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). He received his B.Eng. degree from the University of Chinese Academy of Sciences in 2019 and his Ph.D. degree from ICT, CAS in 2025. He is a core developer of the XiangShan open-source high-performance RISC-V processor, where he has pioneered several agile design and verification techniques that have been successfully integrated into the project. His work has been recognized with the CAS President’s Special Award, the ICT Director’s Special Award (Xia Peisu Award), and the National Scholarship. His research contributions have been published in leading venues such as MICRO, HPCA, DAC, and JCST. Notably, XiangShan and its agile design methodology were selected as one of 2022 IEEE Micro Top Picks, recognizing it as one of the year’s most influential conference papers to computer architecture.