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UID:pretalx-eu-summit-2026-QVKCU9@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T124500
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DESCRIPTION:The growing complexity of RISC-V processors\, driven by rapidly
  expanding ISA extensions and sophisticated microarchitectures\, has made 
 functional verification a dominant bottleneck. Contemporary CPU verificati
 on commonly relies on RTL co-simulation against a software reference model
 \, but on hardware-assisted simulation platforms (e.g.\, FPGAs) this workf
 low is fundamentally limited by high-volume communication between the acce
 lerated RTL and the host-executed reference\, preventing verification thro
 ughput from scaling. This paper addresses this by eliminating the RTL-host
  interaction bottleneck and proposing a Synthesizable Verification Methodo
 logy (SVM). We re-architect a RISC-V reference model as synthesizable hard
 ware and deploy it alongside the design under test on the same acceleratio
 n platform\, enabling fully hardware-based co-simulation at near-native sp
 eeds (60 MHz on FPGAs) while preserving reference-model checking and debug
  observability.
DTSTAMP:20260522T163549Z
LOCATION:Plenary
SUMMARY:SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification 
 - Yinan Xu
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/QVKCU9/
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