Hardware Description Languages (HDLs) have evolved from traditional Register Transfer Level (RTL) modeling over High-level Synthesis (HLS) towards todays generative approaches. Although modern HDLs often assert technical advantages, directly comparable evaluations across HDL paradigms remain scarce.
This work introduces a year-long, community-driven tournament, designed to enable reproducible comparison of HDLs under uniform conditions. A RISC-V microarchitecture is independently implemented in multiple HDLs and evaluated within a standardized, GitHub-based framework. Since the framework provides identical conditions, differences can be related to how an HDL enables hardware realization. To ensure the quality of this tournament, all results are public, reproducible, and objectively evaluated, providing transparent evidence of HDL-specific strengths and trade-offs. Through contribution, participants can systematically demonstrate the capabilities of their preferred HDL. The collected implementations can further be used as common reference basis for research, education, and reproducible comparison of HDL approaches.