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UID:pretalx-eu-summit-2026-R7MK7D@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T174500
DTEND;TZID=CET:20260610T180000
DESCRIPTION:Driven by the need for zonal control architectures in software-
 defined vehicles\, open-source RISC-V cores are becoming a compelling solu
 tion for automotive microprocessor units (MPUs). We introduce a 64b cache-
 coherent\, tightly coupled cluster built upon the industry-backed OpenHW C
 VA6S+ core and HPDCache\, capable of executing SMP Linux and RTOS kernels.
  A design space exploration of the core branch predictor identifies an emb
 edded tournament configuration that reduces its area by 11.6% with no loss
  in accuracy. Evaluated on the Splash-3 benchmark suite\, the cluster achi
 eves a geometric mean speedup of 1.75× over a single-core baseline\, and 
 a 1.21× speedup over a prior implementation based on the scalar CVA6 and 
 legacy cache subsystem. Synthesized in GlobalFoundries' 12 nm FinFET\, the
  dual-core cluster incurs less than 1% per-core area overhead\, with the c
 oherent unit in the interconnect contributing only 35 kGE (1.5%) to the to
 tal cluster footprint.
DTSTAMP:20260522T163537Z
LOCATION:Plenary
SUMMARY:An Open-Source CVA6S+ based High-Performance\, Cache-Coherent Clust
 er for 64b Automotive MPUs - Riccardo Tedeschi
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/R7MK7D/
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