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UID:pretalx-eu-summit-2026-RQP9GP@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T154000
DTEND;TZID=CET:20260609T155000
DESCRIPTION:As RISC-V expands into embedded critical domains like IoT and a
 utomotive automotive require predictable isolation mechanisms. Traditional
  MMU-based virtualization is often impractical for these resource-constrai
 ned environments due to the latency of page-table walks and significant me
 mory overhead. In contrast\, MPU-style region-based protection offers dete
 rministic access checks with minimal footprint\, making physical memory pr
 otection essential for secure\, mixed-criticality systems.\n\nWhile RISC-V
  PMP provides such mechanisms at machine privilege level\, modern embedded
  software stacks\, including RTOSes\, separation kernels\, and lightweight
  hypervisors\, require similar capabilities at supervisor level. The propo
 sed Supervisor-mode Physical Memory Protection (SPMP) extensions address t
 his gap by allowing supervisor software to define access permissions over 
 physical memory regions\, enabling robust compartmentalization of software
  components in systems without virtual memory.\n\nVirtualization further i
 ncreases the need for such mechanisms. Embedded hypervisors are increasing
 ly used to consolidate multiple operating systems or software domains on a
  single microcontroller-class platform while maintaining strict isolation 
 guarantees. To support this model\, SPMP is being extended to interact wit
 h the RISC-V Hypervisor extension through a two-stage protection approach 
 (vSPMP)\, enabling the hypervisor to enforce global isolation while allowi
 ng guest operating systems to manage their own protection domains.\n\nThis
  talk presents the current status of the SPMP and SPMP for Hypervisor spec
 ifications\, their architectural design and rationale\, and their integrat
 ion with the RISC-V privilege architecture. We will discuss the design rat
 ionale\, implementation considerations\, and potential deployment scenario
 s in secure IoT microcontrollers and automotive mixed-criticality systems.
DTSTAMP:20260522T163119Z
LOCATION:Poster Island A
SUMMARY:Memory Protection for MMU-less RISC-V: Current Status of SPMP and v
 SPMP - joseosyx
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/RQP9GP/
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