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UID:pretalx-eu-summit-2026-RT7JWV@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T110000
DTEND;TZID=CET:20260609T111000
DESCRIPTION:In modern embedded security architectures\, the Trusted Executi
 on Environment (TEE) serves as the fundamental tool for isolation\, ensuri
 ng that critical assets in applications like Electric Vehicles (EVs) and r
 obotics remain protected from compromised software. However\, restricted b
 y current RISC-V specifications for MCUs\, implementing this isolation typ
 ically imposes a severe penalty on real-time performance due to the prolon
 ged software prologue required for context switching. To resolve this\, we
  present a lightweight 2-mode (M-mode and U-mode) secure-domain-aware RISC
 -V MCU architecture designed for security-sensitive\, real-time applicatio
 ns. This architecture introduces a hardware-managed "Trusted State" (TS) u
 sed to dynamically filter valid enhanced Physical Memory Protection (ePMP)
  entries in U-mode. To eliminate register preservation overhead\, the MCU 
 features a dedicated "Snapshot Buffer" for every General Purpose Register 
 (GPR) and Control and Status Register (CSR) subject to backup. Crucially\,
  the hardware captures the execution context into this buffer in a single 
 cycle\, allowing the CPU to immediately begin executing the Interrupt Serv
 ice Routine (ISR). The captured data is then pushed to an SP-based Data Lo
 cal Memory (DLM) via a 128-bit wide data-path in the background. By overla
 pping this memory write with the ISR's preamble execution\, this design ef
 fectively hides the context save time\, ensuring the system is seamlessly 
 prepared for nested interrupts. This architecture guarantees hardware-enfo
 rced isolation while satisfying the real-time requirement.
DTSTAMP:20260522T163205Z
LOCATION:Poster Island B
SUMMARY:A Low Latency Real-Time RISC-V MCU for TEE - Paul Shan-Chyun Ku
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/RT7JWV/
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