We present an end-to-end framework for the automatic generation of custom RISC-V instruction-subset processors (RISSPs) tailored to machine learning (ML) inference. Building on the RISSP methodology, our fully automated flow accepts model hyperparameters and a target dataset, performs offline training, and generates the complete inference implementation together with all deployment artifacts for the target device. The resulting inference code then drives the RISSP generation, synthesising a custom processor that implements only the RISC-V instructions used by the application. By co-optimizing software and hardware within a tightly integrated co-design toolchain, the combined flow reduces ISA footprint and design complexity, enabling smaller and more energy-efficient processors for ML workloads at the edge.