RETrace EX: Interactive Trace Analysis Framework for RISC-V Hardware Optimization
2026-06-10 , Poster Island B

Identifying the optimal hardware configuration for running complex workloads on edge devices is critical for reducing cost and maximizing performance. Tailoring hardware designs to specific applications significantly increases resource efficiency, which is essential to meet the strict performance constraints. Unfortunately, exploring the design space at the hardware-level is difficult due to the complexity of the hardware design processes.
We present RETrace EX, an interactive analysis framework for identifying profitable hardware optimizations from system-level execution traces. The tool automatically identifies custom ISA extensions and estimates their performance impact as well as the expected area cost. To adjust the optimization goal for arbitrary systems and design capabilities, the user can choose from a range of preset scoring functions or specify a custom one. Applied to a wide range of representative embedded and edge artificial intelligence workloads, we are able to identify individual custom instructions that yield expected performance improvements of up to 32 % for Embench and 60 % for MLPerf Tiny benchmarks. The framework is provided as open source.


This submission presents a new user-friendly framework to identify and design profitable custom RISC-V extensions.

Jan Zielasko is a PhD student at the University of Bremen and a researcher at the Cyber-Physical Systems department of the German Research Center for Artificial Intelligence (DFKI). His research focuses on Virtual Prototype-driven tracing, analysis, verification and hardware optimization.