2026-06-10 –, Poster Island B
This work presents a co-simulation methodology for the evaluation of pixel detector architecture, combining two independently developed tools: PixESL, a virtual prototyping framework targeting the architectural exploration and performance assessment of pixel detector systems, and GVSoC, a full-platform simulator for RISC-V IoT SoCs.
In parallel with PixESL's development, studies on integrating RISC-V-based SoCs with pixel detector readout circuitry were carried out using GVSoC. Rather than relying on fixed ASIC readout architectures, this approach introduces a programmable processing layer alongside the pixel readout, enabling software-level control over data handling.
In the outlined co-simulation flow, PixESL generates data for a given readout architecture and set of stimuli, while GVSoC simulates the target application executing on the PULP RISC-V SoC platform. Additionally, in order to accurately capture the overhead of data movement within this chain, a virtual prototype of the DMA block responsible for transfers between pixel readout and SoC was developed. Together, these components provide a unified view of the full readout chain, from initial stimulus to processed data, opening possibilities for more informed hardware-software co-design in future detectors.
Mihailo Obradovic is an electronics engineer at CERN. His current work focuses on co-simulation methodologies for hardware modelling, with a specific interest in evaluating RISC-V SoC integration into detector readout systems and investigating how open-standard processor architectures can satisfy the performance and reliability constraints typical of high-energy physics applications. Mihailo holds a Bachelor's degree in electronics engineering from the University of Belgrade.