2026-06-10 –, Poster Island C
The PULP Platform team at ETH Zürich and the University of Bologna has delivered several “big” chips based on RISC-V cores that exceed the complexity of chips traditionally designed in academic/research settings. These designs are made possible through open-source principles that allow greater collaboration and innovation in critical parts of the design. RISC-V has been instrumental in the development of these designs, allowing the team to develop a sandbox of building blocks for creating designs that exceed one billion transistors.
This extended abstract presents large-scale RISC-V silicon developed in academia using the PULP Platform at ETH Zürich and the University of Bologna. Over a decade, the platform has produced more than 70 ASICs, including several “big” chips exceeding one billion transistors across 22–7 nm technologies. We discuss four key enablers: open-source design reuse, forming capable design teams, access to funding and advanced technologies/IP, and assembly and packaging for prototype quantities, enabling complex academic silicon tapeouts.
Yichao Zhang received his M.Sc. degree from Nanyang Technological University, Singapore, in 2017. He served as a Physical Design Engineer at MediaTek and as the Lead Application Engineer at Cadence Design Systems in Singapore until 2021.
In 2021, he joined the Integrated Systems Laboratory at ETH Zurich to pursue a Ph.D. under the supervision of Prof. Dr. Luca Benini. As a developer of the Parallel Ultra-Low Power (PULP) platform, his research focuses on physically feasible, ultra-large-scale many-core shared-memory architectures with both scalar and vector processing, leveraging scalable, high-bandwidth, low-latency Network-on-Chip. On the application side, he focuses on software-defined B5G/6G Open Radio Access Networks for programmable baseband Physical Uplink Shared Channel processing.