2026-06-09 –, Poster Island B
Post-Quantum Cryptography (PQC) is moving from algorithm selection to deployment, where performance, energy, and portability are key constraints, especially on embedded and IoT-class processors. Many PQC schemes stress general-purpose cores with large arithmetic workloads and heavy memory traffic. Instruction-set extensions (ISE) offer a practical middle ground: they speed up dominant kernels while preserving programmability.
In this context, we target post-quantum digital signatures, which remain under active evaluation, as reflected by NIST's 2023 call for additional schemes. We focus on CROSS, a code-based signature built from zero-knowledge proofs and the Restricted Syndrome Decoding Problem, and present CIRCE: a RISC-V–integrated extension connected through the Core-V eXtension Interface (CV-X-IF). CIRCE supports both R-SDP and R-SDP(G), runs across all official parameter sets without hardware retuning, and achieves an average 2x speed-up on a Zynq UltraScale+ FPGA with an ultra-compact footprint (down to 800 LUTs / 100 FFs).
Valeria Piscopo received the B.Sc. and M.Sc. degrees in Electronic Engineering from Politecnico di Torino, in 2021 and 2024 respectively. Since November 2024, she is a Ph.D student in Electrical, Electronic and Communications Engineering at Politecnico di Torino. Her research activity is centered on the design of secure hardware accelerators for Post-Quantum Cryptography and their integration in RISC-V ecosystems.
Ph.D. researcher in Electrical/Electronic Engineering with strong organizational skills and high motivation. Experienced in hardware/software co-design for embedded systems, including RISC-V SoC integration, custom accelerator interfaces, RTL development (SystemVerilog), FPGA prototyping, and embedded C. Solid background in Post-Quantum Cryptography implementations and optimization, with a performance-driven mindset and enthusiasm for new technical challenges.