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UID:pretalx-eu-summit-2026-TEUJU8@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T104500
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DESCRIPTION:As cybersecurity threats continue to evolve\, hardware security
  has become a critical issue in the design of electronic devices. The adve
 nt of quantum computing has forced standardization bodies to rethink crypt
 ographic foundations\, leading to the rise of Post-Quantum Cryptography (P
 QC) as a strategic priority. At the same time\, the RISC-V open-source ins
 truction set architecture is emerging as a key enabler of secure hardware\
 , offering new opportunities to design intrinsically secure microarchitect
 ures.\nTo address these research opportunities\, CEA has developed VASCO\,
  an ASIC platform designed to innovate\, implement and characterize secure
  hardware primitives. It supports the development of robust countermeasure
 s against side-channel attacks\, fault injection and other physical securi
 ty threats. In addition\, VASCO Is adopted for characterization of securit
 y primitives such as True Random Numbers Generators (TRNGs) and Physically
  Unclonable Functions (PUFs). VASCO focuses also on PQC\, which requires s
 pecialized hardware accelerators to achieve efficient and secure implement
 ations. This demo will present the latest advancements made with VASCO#3\,
  which was fabricated in 2025.
DTSTAMP:20260715T065913Z
LOCATION:Demo Theater
SUMMARY:VASCO: ASIC Test Platform for Hardware Security on FD-SOI - Stefano
  Di Matteo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/TEUJU8/
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