Compilers play a central role in unlocking the full performance potential of rapidly evolving RISC-V processors. In the practice of optimizing SPEC CPU 2006 and SPEC CPU 2017 using LLVM for RISC-V, a few compiler optimizations targeting RISC-V have been implemented, involving approaches that both enhance the effectiveness of individual optimization passes and refine how passes interact within the optimization pipeline.
This work introduces four such optimizations integrated into LLVM: (1) extending loop interchange to support loops containing reduction patterns, (2) enhancing loop strength reduction for nested loops, (3) eliminating unnecessary loop counters to unlock further optimizations such as loop unroll, and (4) refactoring multi-dimensional array accesses to enable subsequent redundant computation elimination. While motivated by RISC-V performance tuning, the proposed techniques can also benefit other architectures such as x86. Evaluated on SPEC CPU 2006 and SPEC CPU 2017, these improvements achieve performance gains ranging from 6\% to 54\% across Intel i9-11900K, SpacemiT Key Stone K1, and XiangShan KMHv3 platforms.