In RISC-V based systems, a key security mecha-
nism is the Input-Output Physical Memory Protection (IOPMP)
subsystem, which enables controlled access to shared memory
and peripherals by non-core initiators [1]. While the specification
defines functional behavior, the availability of a publicly available
cycle-accurate reference model will encourage early SoC-level
integration.
This paper presents an open-source cycle-accurate IOPMP
reference model consisting of a SystemVerilog wrapper integrated
with a C-based functional reference model. The SystemVer-
ilog wrapper models pipeline timing, transaction ordering, and
standard bus interfaces, while the C-based reference model
provides specification-compliant functional evaluation of address
matching, permission checking, and priority resolution. The
combined architecture enables both functional correctness and
timing-accurate system-level validation.
The model supports AMBA AXI4 for transaction enforcement
and AMBA AHB3-Lite for configuration, to enables seamless re-
placement with actual RTL. A reusable suite of architectural-level
bare-metal tests is provided, and the approach is demonstrated
through integration in an open-source CVA6-based SoC [4].
Index Terms—RISC-V, IOPMP, SoC Security, Reference
Model, Cycle-Accurate Modeling