2026-06-10 –, Poster Island C
This paper presents a radiation-hardened, open-source RISC-V CVA6 core designed for space, aeronautics, and automotive applications, where Single Event Upsets (SEUs) threaten reliability or safety. The design integrates error detection and recovery in L1 caches and Dual-Core Lockstep (DCLS) with temporal diversity. For non-critical workloads, the system supports Asymmetric Multiprocessing (AMP), enabling independent core operation. Tested with Linux and Zephyr, this work is inspired by RISC-V International’s Functional Safety white paper and advances open-source, fault-tolerant computing for critical systems. It is being integrated in a new 18 nm SoC for AI.
Co-authors:
Thales / cortAIx Labs, Palaiseau, France: Jérôme Quévremont, Daniel Gracia Pérez, Abdou Lahat Ndiaye, Julien Mallet
STMicroelectronics, Agrate Brianza, Italy: Paolo Zambotti, Francesco Diodati, Stefano Bosisio
Jérôme Quévremont graduated in telecommunications and electronics in 1995 (Télécom Bretagne, now IMT Atlantique). After developing telecom and security integrated circuits at Texas Instruments and Thales Communications, in 2007 he headed a development lab, specialized in specifying, developing and validating secure- and crypto-chips in ASIC and FPGA technologies. His main expertise is related to ASICs and systems-on-chip in the field of networks, radio, cryptography, hardware-reconfigurable platforms, multi-cores and trusted computing. In March 2020, he joined Thales Research & Technology cortAIx Labs as an architect and a project leader in the field of RISC-V and open hardware, with special interest on embedded efficient computing, functional safety and security.