The transition toward centralized automotive computing platforms demands scalable, high-performance, and energy-efficient AI acceleration tightly integrated with open instruction set architectures. Within the European Chips Joint Undertaking framework, the [PROJECT NAME] project develops a next-generation automotive hardware platform based on RISC-V technology.
This paper explores three hardware acceleration paradigms applicable to RISC-V-based automotive systems: (i) memory-mapped monolithic accelerators, (ii) custom ISA extensions tightly coupled to the processor pipeline, and (iii) Near-Memory Computing (NMC) architectures. We present an ongoing comparative study evaluating their applicability to representative automotive AI kernels, including conventional neural networks (CNNs, MLPs), data-driven battery models, and emerging Spiking Neural Networks (SNNs).
While all paradigms provide workload-dependent performance benefits, preliminary architectural analysis suggests that Near-Memory Computing offers superior scalability and energy efficiency for memory-bound AI workloads. Complementing the hardware effort, we develop a software ecosystem leveraging MLIR-based compilation flows to efficiently map both conventional and neuromorphic models onto heterogeneous RISC-V accelerators.