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UID:pretalx-eu-summit-2026-VRKMGE@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T131000
DTEND;TZID=CET:20260611T132000
DESCRIPTION:The Discrete Cosine Transform (DCT) is a key component in image
  and video compression systems due to its high energy compaction and effic
 ient implementation. This paper presents a hardware accelerator for the 2-
 D DCT integrated into RISC-V–based FPGA systems. The design relies on an
  optimized 8-point 1-D DCT algorithm requiring only 11 multiplications and
  29 additions\, extended to 2-D using row–column decomposition. The acce
 lerator employs a three-stage pipeline performing row-wise transform\, col
 umn-wise transform\, and quantization. It was integrated with both MicroBl
 aze V and CVA6 RISC-V cores and implemented on AMD VCU128 and KCU116 FPGA 
 development boards. Experimental results for multiple image resolutions sh
 ow significant performance improvements compared with the software impleme
 ntation\, achieving speedups of up to 44.56× and a throughput of 2 Mpixel
 /s at 100 MHz. The accelerator uses modest FPGA resources\, enabling multi
 ple instances and demonstrating its suitability for accelerating image and
  video compression pipelines in RISC-V–based systems.
DTSTAMP:20260522T163128Z
LOCATION:Poster Island A
SUMMARY:RISC-V Hardware Accelerator for 2-D Discrete Cosine Transform - And
 rei Stan
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/VRKMGE/
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