2026-06-11 –, Poster Island A
The Discrete Cosine Transform (DCT) is a key component in image and video compression systems due to its high energy compaction and efficient implementation. This paper presents a hardware accelerator for the 2-D DCT integrated into RISC-V–based FPGA systems. The design relies on an optimized 8-point 1-D DCT algorithm requiring only 11 multiplications and 29 additions, extended to 2-D using row–column decomposition. The accelerator employs a three-stage pipeline performing row-wise transform, column-wise transform, and quantization. It was integrated with both MicroBlaze V and CVA6 RISC-V cores and implemented on AMD VCU128 and KCU116 FPGA development boards. Experimental results for multiple image resolutions show significant performance improvements compared with the software implementation, achieving speedups of up to 44.56× and a throughput of 2 Mpixel/s at 100 MHz. The accelerator uses modest FPGA resources, enabling multiple instances and demonstrating its suitability for accelerating image and video compression pipelines in RISC-V–based systems.
ANDREI STAN (Member, IEEE) received the B.S. degree in computer engineering, the M.Sc. degree in advanced computer architecture, and the Ph.D. degree in computer engineering from the ‘‘Gheorghe Asachi’’ Technical University of Iaşi, Romania, in 2002, 2003, and 2012, respectively. He is currently a Faculty Member in the Department of Computer Engineering and actively contributes to both teaching and research in computer systems and embedded systems. His primary research interests include computer architecture and embedded systems. His work explores modern architectures for domain-specific computing, hardware-software co-design methodologies, and system-level modeling.
Cosmin-Andrei Popovici received his B.S. degree in Computer Engineering and Information Technology in 2020 and his M. Sc. degree in Embedded Computers in 2022, both from the Faculty of Automatic Control and Computer Engineering of the "Gheorghe Asachi" Technical University of Iași, România. He is currently pursuing a Ph.D. degree in Computer Engineering from the same university. His research interest focuses on Digital Design, Computer Architecture, especially hardware accelerators and extensions for RISC-V cores, and Embedded Systems. As a graduate teaching assistant and faculty member in the Department of Computer Engineering, he teaches laboratory sessions for the courses of Introduction in Programming (C Language), Data Structures, Computer Architecture, Computer Networks, Systems with Microprocessors and Multiprocessor Systems.