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UID:pretalx-eu-summit-2026-VVBBMK@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T131000
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DESCRIPTION:The rapid expansion of the RISC-V ecosystem has led to an incre
 asing number of open hardware projects hosted on collaborative platforms s
 uch as GitHub. While modern software development benefits from mature cont
 inuous integration and continuous deployment (CI/CD) methodologies\, equiv
 alent automated verification infrastructure remains limited for hardware d
 esign. In particular\, formal verification tools such as logic equivalence
  checking (LEC) remain largely restricted to proprietary EDA solutions.\nT
 his work explores the use of lightweight open-source EDA tools as scalable
  verification agents for open hardware development workflows. We present a
 n open-source logic equivalence checking tool designed to operate efficien
 tly within CI environments for RISC-V projects. Built on a high-performanc
 e C++ infrastructure for netlist representation and analysis\, the tool en
 ables rapid equivalence verification between different RTL transformations
  and synthesized netlists. Experimental results on open RISC-V designs dem
 onstrate that automated equivalence checks can be integrated into CI pipel
 ines with execution times compatible with typical pull request validation 
 workflows. This approach provides a practical first verification gate for 
 open hardware repositories before deeper sign-off verification using comme
 rcial tools.
DTSTAMP:20260522T163128Z
LOCATION:Poster Island A
SUMMARY:kepler-formal: Open Logic Equivalence Checking for RISC-V CI Workfl
 ows - Christophe Alexandre\, Noam Cohen
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/VVBBMK/
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