2026-06-10 –, Poster Island A
In recent years, the executable specification generated from Sail-RISC-V has increasingly been considered as a successor to the widely used Spike ISA Simulator as golden reference for RISC-V, including the complex and highly configurable RISC-V Vector Extension (RVV). In this paper, we compare the RVV behavior of Sail-RISC-V against Spike using the automated testing framework RVVTS. While Sail-RISC-V largely matches Spike under positive testing (0.23% deviations), negative testing reveals substantially more deviations (3.73%), highlighting remaining issues in Sail-RISC-V’s RVV instruction validity checking under dynamic configurations.
Manfred Schlägl is a PhD student at the Institute for Complex Systems, JKU Linz, under Prof. Daniel Große. For 15 years, he worked in industry, focusing mainly on low-level firmware and operating systems for industrial embedded systems. In 2021, he left the industry to resume his studies, completed his Master's degree in Computer Science in 2023, and started his PhD immediately afterward. His main research interests are hardware/software co-simulation using virtual prototypes and hardware verification. He is also deeply interested in operating systems, hardware platforms, and computer architectures, especially RISC-V.