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UID:pretalx-eu-summit-2026-XFYMDU@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T171500
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DESCRIPTION:The RISC-V SPMP for Hypervisor specification enable MMU-less vi
 rtualization through a multi-layered memory protection architecture. While
  this model provides strong isolation for mixed-criticality MCUs\, concern
 s have been raised regarding the hardware overhead and timing impact of mu
 ltiple PMP layers. In this work\, we present an empirical evaluation of an
  SPMP for Hypervisor proof-of-concept implementation. We analyze FPGA reso
 urce utilization and timing behavior as a function of entry count and disc
 uss realistic entry requirements for MCU-based virtualization workloads\, 
 providing insights for hardware designers adopting SPMP-based architecture
 s.
DTSTAMP:20260522T163211Z
LOCATION:Plenary
SUMMARY:Practical Implications of SPMP-Based Virtualization in RISC-V - Man
 uel Rodríguez
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/XFYMDU/
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