2026-06-10 –, Poster Island C
The Monte Cimone project provides a RISC-V testbed for High-Performacne Computing cluster. This paper presents Monte Cimone v3 (MCv3), the third iteration of the Monte Cimone RISC-V HPC cluster, integrating the SOPHGO Sophon SG2044 processor, an evolution of the SG2042 used in MCv2. We characterize MCv3 using HPL and STREAM benchmarks coupled with power measurements, and compare it against two reference platforms: the Intel Xeon Platinum 8480+ (Sapphire Rapids) and the NVIDIA Grace CPU Superchip. Our results show that the SG2044 more than doubles single-core performance and improves scalability compared to SG2042. MCv3 achieves an energy efficiency of 3.08GFLOPs/W which improves of 10x w.r.t. MCv1 and is in the range of x86-64 and Arm servers. On pure performance when normalized on the SIMD/Vector length MCv3 on its peak efficiency point (16 cores) achieves 46% performance of Intel Sapphire Rapids server and 91% performance of NVIDIA Grace CPU superchip.
I am a PhD student at the ECS Lab at University of Bologna, where I also earned my MSc in Electronics Engineering. My research focuses on digital architectures, with particular interest in RISC-V vector and matrix extensions and processing-in-memory (PIM) systems. I work on the Monte Cimone project, contributing to the enablement and characterization of the second-generation RISC-V cluster while evaluating the third iteration. I also contributed to AME-PIM, a novel approach that exposes PIM capabilities through the semantics of a matrix extension. In parallel, I work within the DARE project, where I contribute to the delivery of ControlPULP as the power-management controller for the GPP subsystem.