This paper introduces the Bicameral+, an enhanced version of the Bicameral Cache; a vector-aware memory hierarchy that separates vector and scalar accesses into two cache partitions tailored to the needs of each kind of access, improving spatial locality for vectors and eliminating scalar interference. The new design aims to reduce implementation complexity and improve energy efficiency, while retaining the performance improvements of the original proposal, by introducing a set associative design and an alternative opportunistic dirty block management scheme. Experimental results on thirteen benchmarks across various configurations show a 7x area reduction and 18x energy savings, while retaining an average 1.59x speedup w.r.t a conventional cache.