RISC-V provides an open and extensible ISA foundation, but its adoption in desktop and server environments remains limited by the existing x86-64 software ecosystem. Dynamic binary translation (DBT) is a practical compatibility layer, yet translating CISC-style x86-64 binaries to RV64 often introduces substantial dynamic instruction-count inflation. Reducing translated instruction count is a necessary first-order condition for improving DBT performance when CPI and frequency changes are bounded. This paper presents a micro-op-guided methodology for analyzing and reducing x86-64-to-RV64 translation overhead. We use x86 micro-ops as a reference for the intrinsic execution complexity of source instructions. This allows us to distinguish unavoidable CISC instruction complexity from additional semantic compensation introduced by cross-ISA translation. Based on this model, we estimate optimistic instruction-count lower bounds for specific optimization classes and identify indirect control-flow resolution as a major source of semantic inflation. We then propose a lightweight Jump Table Cache (JTC) extension for RISC-V and evaluate it in gem5. A 1024-entry, 4-way JTC achieves over 90% hit rates on most SPECint workloads and reduces estimated execution cycles by 6.0%--14.6%.