RISC-V is rapidly emerging as an open and extensible ISA, yet its adoption in desktop and server environments remains constrained by the dominance of the x86-64 software ecosystem. Dynamic binary translation (DBT) provides a practical mechanism for executing legacy x86-64 binaries on RISC-V without source code, but purely software-based DBT often incurs substantial overhead. In this work, we investigate a hardware/software co-designed approach for user-level x64-to-RV64 translation. We begin with a fine-grained characterization of runtime instruction behavior from SPEC CPU 2017 benchmarks, and extract micro-operation (μop) information for different instruction variants on a representative x86 microarchitecture. By correlating dynamic execution profiles with μop-level complexity, we introduce a quantitative model of semantic inflation, which exposes the semantic gap introduced by cross-ISA translation by discounting the inherent execution complexity of CISC instructions. This model enables us to systematically identify instruction variants that exhibit disproportionate expansion and reveals the underlying causes of this bloat. Based on these insights, we propose targeted hardware extensions to mitigate translation overhead. We implement the proposed approach in a Box64-based prototype and evaluate it through QEMU-based simulation. Experimental results demonstrate a significant reduction in the number of translated instructions, indicating a practical path toward near-native cross-ISA execution efficiency.