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UID:pretalx-eu-summit-2026-YCVWTV@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T103000
DTEND;TZID=CET:20260611T104000
DESCRIPTION:The RISC-V Vector Extension (RVV) adopts a vector-length agnost
 ic (VLA) model for exploiting data-level parallelism. We argue that this a
 bstraction imposes significant costs in real silicon: control logic comple
 xity\, implicit state tracking in out-of-order pipelines\, and runtime ove
 rhead that erode VLA’s theoretical portability benefits. Drawing on prod
 uction experience with the ET-SoC-1\, a 1088-core\nRISC-V processor\, we p
 resent ET-SIMD\, a fixed-width 256-bit packed SIMD extension that overlays
  the standard F extension register file. In Flynn’s Taxonomy [2]\, ET-SI
 MD is a classical SIMD design: scalar and packed instructions share the sa
 me register file\, a pattern well understood by GCC and LLVM autovectorize
 rs and proven on competing ISAs\, yet absent from RISC-V. We describe the 
  extension’s architectural rationale\, its relationship to contemporary 
 packed SIMD practice\, and its availability through the AI Foundry initiat
 ive.
DTSTAMP:20260522T163558Z
LOCATION:Poster Island C
SUMMARY:Towards a Modern Packed SIMD Architecture for RISC-V: Learning from
  Production Of ET-SIMD - FelixCLC
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/YCVWTV/
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