The RISC-V Vector Extension (RVV) adopts a vector-length agnostic (VLA) model for exploiting data-level parallelism. We argue that this abstraction imposes significant costs in real silicon: control logic complexity, implicit state tracking in out-of-order pipelines, and runtime overhead that erode VLA’s theoretical portability benefits. Drawing on production experience with the ET-SoC-1, a 1088-core
RISC-V processor, we present ET-SIMD, a fixed-width 256-bit packed SIMD extension that overlays the standard F extension register file. In Flynn’s Taxonomy [2], ET-SIMD is a classical SIMD design: scalar and packed instructions share the same register file, a pattern well understood by GCC and LLVM autovectorizers and proven on competing ISAs, yet absent from RISC-V. We describe the extension’s architectural rationale, its relationship to contemporary packed SIMD practice, and its availability through the AI Foundry initiative.