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UID:pretalx-eu-summit-2026-YXSRKX@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T105000
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DESCRIPTION:CVA6 is an open-source RISC-V core with highly configurable par
 ameters for tailoring the core to various\napplications. An optimization-o
 riented analysis of the current implementation showed that the scoreboard 
 (SB) and controller are the biggest combinational modules involved in the 
 critical path. The SB is in charge of many crucial functions\, including i
 ssuing\, forwarding\, writeback\, and committing\, while the controller ma
 nages all the stages of the core. This work presents two optimization prop
 osals:  re-order buffer (ROB) and Issue logic separation from the Scoreboa
 rd and registering Controller output. Preliminary results show promising o
 utcomes in implementing the core\, relaxing the timing\, which in turn ena
 bles operating at a higher frequency. With this optimization\, we get to i
 mprove the maximum frequency of operation by 14% for the existing FPGA con
 figuration from OpenHW for Xilinx FPGA.
DTSTAMP:20260522T163211Z
LOCATION:Poster Island D
SUMMARY:CVA6 Optimization - Udaya Subedi\, Angela Gonzalez
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/YXSRKX/
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