BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//cfp.riscv-europe.org//eu-summit-2026//talk//ZBWEM7
BEGIN:VTIMEZONE
TZID:CET
BEGIN:STANDARD
DTSTART:20001029T040000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000326T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-ZBWEM7@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T132000
DTEND;TZID=CET:20260609T133000
DESCRIPTION:IPECC\, an open-source side-channel-resistant ECC hardware acce
 lerator developed by the French national agency ANSSI\, is integrated into
  the CVA6 RISC-V SoC and prototyped on a Genesys 2 (XC7K325T) FPGA. Using 
 the libecc cryptographic library\, we evaluate eight signature scheme/curv
 e combinations in three configurations: software-only execution\, hardware
  acceleration without countermeasures\, and fully protected hardware accel
 eration. With all countermeasures active\, IPECC reduces ECDSA P-256 signa
 ture latency from 1.13 s to 180 ms (a 6.3x speedup)\, reaching 7.8x for Sc
 hnorr-based schemes and scaling up to 9.1x for P-521. On the FPGA target\,
  the countermeasure overhead varies drastically from +3% (hash-dominated E
 dDSA) to +279% (Schnorr-based schemes). We demonstrate that this variance 
 is fundamentally driven by the physical True Random Number Generator (TRNG
 ) latency and each protocol’s specific reliance on scalar multiplication
 . In its compact P-256 configuration\, the accelerator occupies only 4.2% 
 of the FPGA LUT fabric (3\,602 LUTs\, 12 DSP48E1). This platform provides 
 a reproducible basis for benchmarking ECC acceleration and side-channel co
 untermeasures on RISC-V SoCs.
DTSTAMP:20260522T163212Z
LOCATION:Poster Island B
SUMMARY:ANSSI IPECC-Accelerated ECC on CVA6 RISC-V SoC: Integration and Ben
 chmarking - IGHILAHRIZ Billal
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBWEM7/
END:VEVENT
END:VCALENDAR