BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//cfp.riscv-europe.org//eu-summit-2026//talk//ZFT38M
BEGIN:VTIMEZONE
TZID:CET
BEGIN:STANDARD
DTSTART:20001029T040000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000326T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-ZFT38M@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T140000
DTEND;TZID=CET:20260610T141000
DESCRIPTION:Domain-Specific architectures with accelerators for machine lea
 rning and signal processing require efficient bulk data movement and high-
 bandwidth access to large datasets. Such capabilities are often absent fro
 m minimal open-source microcontrollers (MCUs). \nWe present HyperCroc\, an
  extension to the end-to-end open-source RISC-V Croc system-on-chip (SoC) 
 integrating a silicon-proven HyperBus controller for off-chip DRAM and Fla
 sh memory access and a DMA engine\, providing a practical MCU-class platfo
 rm with streamlined plug-in support for domain-specific acceleration. Hype
 rBus offers a low-pin-count PSDRAM interface at up to 400 MB/s\, enabling 
 bandwidth-scaled dataset access\, while the DMA engine enables autonomous\
 , high-throughput transfers without CPU intervention. HyperCroc preserves 
 Croc’s open-source synthesis and physical implementation flow targeting 
 IHP’s open 130 nm process design kit (PDK)\; the full chip can be implem
 ented in under one hour on a consumer-grade workstation. \nWe further repo
 rt first silicon measurements from MLEM\, the first Croc tapeout\, confirm
 ing that the silicon is fully functional at 72 MHz @ 1.2 V and validating 
 the end-to-end flow.
DTSTAMP:20260715T065845Z
LOCATION:Poster Island C
SUMMARY:HyperCroc: Open-Source RISC-V MCU with Plug-In Interface for Domain
 -Specific Accelerators - Philippe Sauter
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ZFT38M/
END:VEVENT
END:VCALENDAR