2026-06-09 –, Poster Island A
As digital systems become ever more interconnected, the global cost of cybercrime continues its steep rise. 70% of the vulnerabilities leading to these attacks stem from memory safety issues, which have remained persistent for several decades. After 15 years of research, the Capability Hardware Enhanced RISC Instructions (CHERI) technology has matured into a practical solution to this challenge now moving toward standardization within RISC-V.
While CHERI has been validated through extensive academic research and multiple industrial prototypes, the next critical step is a broad, sustainable transfer from research labs into commercial RISC-V products. This paper outlines how collaborative ecosystem building—across academia, industry, open-source communities, and government stakeholders—is essential to enable the adoption of CHERI on RISC-V. The CHERI Alliance plays a central role in this transition, acting as a bridge, amplifier, and catalyst for a memory safe ecosystem.
Real-life experience of a transfer from academia to industry
Mike Eftimakis brings three decades of experience in the semiconductor and electronics industry, having held senior technical and business leadership roles throughout his career. He has contributed to innovation and growth at companies such as VLSI Technology, NewLogic, Arm, and Codasip, and has also founded and led his own company. His expertise ranges from chip design engineering and system architecture to product and company management, marketing and strategy, making him a key contributor to the growth and success of microelectronics organisations.
He is a Founding Director of the CHERI Alliance, a non-profit industry association dedicated to accelerating the adoption of CHERI technology. This technology addresses the root causes of most current cyberattacks, contributing to a safer and more trustworthy digital world.