2026-06-10 –, Poster Island C
This work presents a novel, highly integrated dual-core microcontroller architecture based on the RISC-V ISA, specifically designed for First Person View(FPV) Drone On-Screen Display (OSD) systems. Traditional solutions suffer from computational bottlenecks or multi-chip synchronization latency. By leveraging a specialized RISC-V asymmetric dual-core architecture, this design achieves sub-microsecond synchronization between complex flight control execution and high-framerate video rendering. Incorporating advanced ISA extensions and custom microarchitectural features, the proposed SoC successfully injects rendered OSD data during the video signal's blanking period with pixel-level precision, showcasing the potential of RISC-V in mission-critical vertical application domains.
In the rapidly evolving field of Drones and edge robotics, First-Person View (FPV) and real-time On-Screen Display (OSD) are mission-critical for flight safety and situational awareness. Historically, embedded systems have relied on dedicated external OSD driver ASICs (such as the legacy MAX7456) or complex discrete analog circuits. These conventional solutions not only increase the Bill of Materials (BOM) cost and printed circuit board (PCB) footprint but also introduce unacceptable detection errors during the blanking intervals of high-definition (e.g., 1080p@60fps) video streams.
Conversely, utilizing a conventional single-core microcontroller to simultaneously handle intensive multi-axis flight dynamics algorithms and highly deterministic pixel-level video rendering inevitably leads to computational bottlenecks and catastrophic frame tearing. While multi-chip processing alternatives exist, they introduce inter-chip synchronization latency and elevated power consumption. This extended abstract introduces a highly integrated, single-chip solution that fully exploits the architectural flexibility of the RISC-V ecosystem. By deploying an asymmetric dual-core topology tailored for hard-real-time execution and video processing, this work addresses the stringent timing requirements of aerospace embedded systems and provides a robust hardware-software co-design reference for the RISC-V community.
Yong Yang received his Ph.D. in Engineering and holds the title of vice Professor. He is the Vice General Manager and Board Member of WCH (Nanjing Qinheng Microelectronics), and Chairman of the Nanjing RISC-V Microcontroller Research Institute. He was the inaugural Vice-Chair of the RISC-V International Certification Steering Committee (CSC). He also serves as an off-campus supervisor at Southeast University and an Industry Professor of Jiangsu Province. With over a decade of R&D experience in embedded systems and IoT integrated circuits, he has spearheaded the design and mass production of proprietary RISC-V MCUs, Bluetooth Low Energy (BLE) SoCs, and USB 3.0 SuperSpeed chips. His technical expertise spans RISC-V ISA, processor microarchitecture, RISC-V Domain-Specific Architectures (DSA), interrupt controllers, and RF transceivers and Antenna design.