2026-06-09 –, Poster Island A
Side-channel attacks leveraging microarchitectural features are well-studied on x86 and ARM, but less so on RISC-V. This work implements and evaluates Flush+Reload cache-side-channel attacks on user-space software in a RISC-V system simulated in gem5 full-system mode. We develop both eviction-based and cache-block-invalidate (cbo.inval) probes, establishing an attack methodology for an unprivileged process using the RISC-V cycle counter. Our experiments reveal timing differences between cached and evicted accesses, confirming the existence of exploitable timing channels. While key recovery remains partial, these results demonstrate the feasibility of cache side-channel attacks on RISC-V and validate gem5 as an effective platform for microarchitectural security research.
Sadia Shamas is a PhD student in the National PhD. Program in Cybersecurity at IMT Lucca and Politecnico di Torino, Italy. Her research focuses on hardware and system security, with particular emphasis on cache side-channel attacks on RISC-V. She received her master's degree in Computer Science from Lahore University of Management Sciences, Lahore, Pakistan, where her master’s thesis focused on developing an energy estimation framework for embedded processors using a hybrid instruction and functional-level power/energy analysis approach. Her current research investigates the potential for side-channel attacks in RISC-V cryptographic implementations using a simulation environment.
Stefano Di Carlo is a full professor of computer engineering at Politecnico di Torino, Department of Control and Computer Engineering, Italy. He received his Ph.D. and M.S. degrees in Computer Engineering from Politecnico di Torino in 1999 and 2003, respectively.
He has authored over 300 publications in major journals and conference proceedings on a wide range of topics. Major topics include dependable computing, artificial intelligence systems, and computational biology. His current research interests include emerging computing paradigms for reliable, energy-efficient computing; computer architectures; neuromorphic computing; systems; and computational biology.
