2026-06-09 –, Poster Island B
This paper introduces HORCRUX, an open RISC-V instruction set extension for post-quantum cryptography (PQC). A modular PQ-ALU, integrated through the Core-V eXtension Interface (CV-X-IF) accelerates the core kernels shared by hash-, lattice-, and code-based schemes, including Keccak processing, sampling, modular/polynomial arithmetic, finite-field operations, and coefficient compression. The design targets NIST-standardized algorithms (ML-KEM, ML-DSA, SLH-DSA, HQC) and additional candidates under evaluation. We release the complete hardware/software stack as open source and report 65 nm ASIC post-synthesis results: with a compact footprint of ~26.3 kGE and energy savings up to 99.5%, the extension provides a practical route to energy-efficient PQC on RISC-V with minimal integration effort.
We present a PQC instruction-set extension that prioritizes kernel-level reuse over per-algorithm specialization. The design identifies the recurring computational patterns that dominate PQC workloads and maps them onto a compact set of custom operations executed by a dedicated PQC arithmetic unit. The same accelerated building blocks support NIST-standardized schemes as well as a wider set of candidate designs, without requiring RTL modifications to the host CPU.
HORCRUX is implemented in a 65 nm CMOS ASIC flow at 100 MHz, with a synthesized area of 26.3 kGE (less than 2% of the host SoC). Each custom instruction is validated through dedicated micro-tests to capture realistic switching activity; post-synthesis power is estimated with Synopsys PrimePower and combined with measured cycle counts to derive energy per operation. Across the full kernel suite, the proposed instructions deliver approximately 5× average speedup over the software baseline and 47% average energy reduction, up to 99.5% for Karatsuba primitve. Overall, HORCRUX achieves a compact, PQC-ISE that provides consistent acceleration and energy savings across heterogeneous PQC families.
Valeria Piscopo received the B.Sc. and M.Sc. degrees in Electronic Engineering from Politecnico di Torino, in 2021 and 2024 respectively. Since November 2024, she is a Ph.D student in Electrical, Electronic and Communications Engineering at Politecnico di Torino. Her research activity is centered on the design of secure hardware accelerators for Post-Quantum Cryptography and their integration in RISC-V ecosystems.
Ph.D. researcher in Electrical/Electronic Engineering with strong organizational skills and high motivation. Experienced in hardware/software co-design for embedded systems, including RISC-V SoC integration, custom accelerator interfaces, RTL development (SystemVerilog), FPGA prototyping, and embedded C. Solid background in Post-Quantum Cryptography implementations and optimization, with a performance-driven mindset and enthusiasm for new technical challenges.